Do you share a passion for bringing new wireless technologies to the rapidly growing mobile market ?

Our client, is a leading telecommunications solutions provider. Through continuous customer-centric innovation, the company has established end-to-end advantages in telecom network infrastructure, applications and software, professional services and devices. Operating in more than 100 countries and serving 45 of the world's top 50 telecom operators and one-third of the world's population.

The European “hardware” R&D centre (based in Leuven) develops next generation RF transceivers, supporting 4G (LTE) and 5G protocols. They are currently looking for a Senior Digital IC Design & verification Engineer to join the creation of the next generation mobile phone chips.

The position

This role includes technical hands-on expertise and excellent team skills; together with his/her team members, this candidate targets high and challenging standards on technical performance, product and process quality and project schedule. This profile is very much oriented at front-end verification and design.


You hold a MSEE or equivalent with +3yr industrial experience designing for ASIC. You can verify and design systems of low to moderate complexity with the support of an experienced team. Experience with back-end related topics such as LEC and STA is a plus.

Technical skills

Synchronous Verilog design targeted at ASIC’s

  • Writing Verilog and SystemVerilog RTL
  • Running a simulator (Cadence, Synopsys, Mentor), visualizing waveforms, general design analysis and debug

Knowledge of module, subsystem and toplevel verification

  • Hands-on experience with writing and maintaining tests in a UVM flow
  • Simulation based coverage (automated and functional)
  • Assertion based verification (ABV)
  • Experience with lint, CDC and formal verification is a plus

Able to write implementation specification and define micro-architectures based on functional specification in close cooperation with analog and system architects

Knowledgeable about concepts such as pipelining, retiming and digital power optimization

Able to work in a Linux environment

  • Python, Perl, TCL scripting
  • Makefiles
  • Shell scripts
  • C/C++/SystemC coding and debug

Experience with revision control systems such as SVN, GIT, Perforce

Experience with (the implementation of) simple DSP algorithms is a plus

  • FIR, IIR, FFT, interpolation
  • Upsampling and downsampling

You have excellent analytical skills and you are result-driven. You have excellent communication skills and you’re a team-player. You also have an eye for process and detail. You are determined, detail-oriented and like new challenges. You are conducting a continuous strive for improvement in circuits and process.

If you recognize yourself in this description, please contact us!

The company offers you a very attractive (personalised) salary package with a very stimulating challenge.

Send us your application (CV, motivations, salary expectations, availability) to Adoc Talent Management (