Do you share a passion for bringing new wireless technologies to the rapidly growing mobile market ?

Our client, is a leading telecommunications solutions provider. Through continuous customer-centric innovation, the company has established end-to-end advantages in telecom network infrastructure, applications and software, professional services and devices. Operating in more than 100 countries and serving 45 of the world's top 50 telecom operators and one-third of the world's population.

The European “hardware” R&D centre (based in Leuven) develops next generation RF transceivers, supporting 4G (LTE) and 5G protocols. They are currently looking for a Senior RFIC Layout Engineer to join the creation of the next generation mobile phone chips.

You hold a Industry degree (MS EE degree, a PhD is an asset) with a strong background in RF Layout in the sub 10-Ghz range , with (around 10 years of) strong & relevant experience in industry and a FinFET experience.

Your broad and well-established technical skills from your experience as an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology. Your expertise allow you to have a good understanding of the different circuit topologies and their constraints for the layout implementation.

You will collaborate closely with the RF designers. You also have a fine understanding of the layout & design rules enables to optimize the implementation.

You have excellent communication skills and you’re a team-player. You also have an eye for process and detail. You are determined and like new challenges.

If you recognize yourself in this description, please contact us!

The company offers you a very attractive (personalised) salary package with a very stimulating challenge.

Send us your application (CV, motivations, salary expectations, availability) to Adoc Talent Management (www.adoc-tm.com).