Do you share a passion for bringing new wireless technologies to the rapidly growing mobile market ?

Our client, is a leading telecom solutions provider, active in several fields where new technologies are key. Through continuous customer-centric innovation, the company has established end-to-end advantages in telecom network infrastructure, applications and software, professional services and devices. Operating in more than 100 countries and serving 45 of the world's top 50 telecom operators and one-third of the world's population.

Their European R&D team develops next generation RF transceivers, supporting 4G (LTE) and 5G protocols.

Today, they are seeking team players who get things done and share a passion for bringing new wireless technologies to the rapidly growing mobile market. Now is your chance to join the engineering team and develop new, world-leading products.

Job responsibilities include:

The company is offering a senior layout engineer position enabling you to join the creation of the next generation mobile phone chips.

The Senior Analog IC Layout Engineer will be part of an experienced layout team. In close cooperation with his colleagues he will be in charge of the layout of high speed analog and RF circuits and he will take up a leading role in the floorplanning and optimization of the system on chip.

He is an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology. The successful candidate will work closely with the RF designers. He/she will take into account the constraints from the designer and will go through iterations with the designer to further optimize the layout from a performance and area perspective.

RF circuit layout experience in the sub 10-Ghz range is mandatory.

The layout engineer should have a good understanding of the different circuit topologies and their constraints for the layout. implementation. Good understanding of the layout rules enables to optimize the implementation.

The senior layout engineer is also capable to perform extraction of parasitic and make the interpretation of these results in view of further optimization.

Position Requirements:

  • Industry Degree qualified (BS or MS EE degree)
  • Ample experience with the Cadence OA VirtuosoXL
  • Experience with RFIC layout (GHz range) in CMOS technology
  • Finfet experience is a major plus.
  • Automation for layout is a plus.
  • Good communication skills & team-player.
  • Process oriented, ability to structure the RF layout process
  • Continuous strive for improvement in circuits and process.
  • Detail oriented and determined
  • Relocation to Belgium, if applicable, is strongly recommended.
  • Excellent written and oral English and local language

If you are interested in taking up the challenge, please send us your application (CV, motivations, salary expectations, availability) to Adoc Talent Management (www.adoc-tm.com).